/*
 * JZ4775 pll configuration
 *
 * Copyright (c) 2013 Ingenic Semiconductor Co.,Ltd
 * Author: Zoro <ykli@ingenic.cn>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/jz4775.h>

void pll_init(void)
{
	void __iomem *cpm_regs = (void __iomem *)CPM_BASE;

	/* Init SEL and DIV */
	writel(0x95700000, cpm_regs + CPM_CPCCR);

#ifdef CONFIG_SYS_APLL_MNOD
	/* Init APLL */
	writel(0xa9000120, cpm_regs + CPM_CPAPCR);
	while(!(readl(cpm_regs + CPM_CPAPCR) & (1 << 10)));
#else
	/* Disable APLL */
	writel(0, cpm_regs + CPM_CPAPCR);
#endif

#ifdef CONFIG_SYS_MPLL_MNOD
	/* Init MPLL */
	writel(CONFIG_SYS_MPLL_MNOD | (1 << 7), cpm_regs + CPM_CPMPCR);
	while(!(readl(cpm_regs + CPM_CPMPCR) & (1 << 0)));
#else
	/* Disable MPLL */
	writel(0, cpm_regs + CPM_CPMPCR);
#endif

	/* Change DIV 改变低20位 改变分频值 */
	writel(0x95794410, cpm_regs + CPM_CPCCR);
	while(readl(cpm_regs + CPM_CPCSR) & (7 << 0));

	/* Change SEL 改变高8位 选择时钟源 */
	writel(0x5a794410, cpm_regs + CPM_CPCCR);
	while(readl(cpm_regs + CPM_CPCSR) & (7 << 0));
}
